This invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to novel and improved decoupling capacitors especially suitable for use in conjunction with Pin Grid Array (PGA) and Plastic Leaded Chip Carrier (PLCC) type integrated circuit packages.
It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. Generally, the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit is accomplished by connecting a decoupling capacitor between the power and the ground leads of the IC.
One connection scheme which has been found to be quite successful is to mount a decoupling capacitor underneath an integrated circuit. Such decoupling capacitors are commercially available from Rogers Corporation, (assignee of the present application) and are sold under the trademark MICRO Q. Examples of these decoupling capacitors are found in U.S. Pat. Nos. 4,475,143, 4,502,101, and 4,748,537, all of which are assigned to the assignee hereof.
U.S. Pat. Nos. 4,626,958, 4,667,267, 4,658,327, 4,734,818 and 4,734,819 are also assigned to the assignee hereof and incorporated herein by reference. These patents disclose decoupling capacitors which are particularly well suited for pin grid array and plastic leaded chip carrier packages. For example, the PGA decoupling capacitor of U.S. Pat. No. 4,626,958 comprises a dielectric material sandwiched between a pair of conductors. A plurality of leads are provided along the periphery of each conductor. These leads extend outwardly a short distance generally in the plane of the metal conductors to which they are attached and are then bent downwardly so as to extend in a direction which is perpendicular to the planes of the conductors. The entire assembly, with the exception of the plural transversely extending lead portions, may then be encapsulated within a suitable non-conductive material.
This flat decoupling capacitor adapted for mounting directly under a Pin Grid Array package will result in a lower decoupling loop, thus providing a more effective decoupling scheme. The capacitor of U.S. Pat. No. 4,626,958 also contributes to a savings in board space, i.e. takes up less "real estate" on the printed circuit board, by resting entirely under the PGA package.
It will be appreciated that the decoupling capacitor of U.S. Pat. No. 4,626,958 features a multiplicity of elongated leads for (1) reduced lead inductance; and (2) increased current capability. Similarly, the decoupling capacitor for PLCC's disclosed in U.S. Pat. Nos. 4,658,327 and 4,734,818 also feature a multiplicity of elongated leads for reducing lead inductance and increasing current capability.
While suitable for its intended purposes, the use of a multiplicity of discrete elongated leads does pose certain drawbacks and practical limitations. An important drawback is that the larger the number of elongated leads, the lower the reduction rate of inductance. Thus, the greater the number of leads, the lower the inductance but only to a point, beyond which, no significant reduction of inductance is achieved and another problem is created. This other problem is that the use of a large number of leads necessitates the burdensome provision of adequate numbers of holes in the printed circuit board.